The invention is directed to an improved approach for implementing cell modeling and selection of cells for electronic designs.
An electronic design, such as the design of a semiconductor integrated circuit (IC), has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer.
Many phases of physical design may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language. An EDA system typically receives the high level behavior descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction using a computer synthesis process. A netlist describes interconnections of nodes and components on the chip and includes information of circuit primitives such as transistors and diodes, their sizes and interconnections, for example.
An integrated circuit designer may use a set of layout EDA application programs to create a physical integrated circuit design layout from a logical circuit design. The layout EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes. After an integrated circuit designer has created an initial integrated circuit layout, the integrated circuit designer then verifies and optimizes the integrated circuit layout using a set of EDA testing and analysis tools. Verification may include, for example, design rule checking to verify compliance with rules established for various IC parameters.
Historically, the design of most IC chips was created from scratch. There was very little design re-use, as most design objects were newly created for each new electronics design. In recent years, re-use of design blocks and cells have become more and more prevalent in the electronics design and manufacturing industry. In many cases, a new design is no longer created from scratch. Instead, the design engineers will start from a previous design, and re-use a significant portion of the previous design to create the new electronics design. Indeed, the design engineer may re-use a vast majority of the previous design, and only add a small proportion of new logic to create the new design. In addition, the re-used portion of the new design may need to be addressed to target new process technology, which may cause new requirements in terms of performance, power, etc.
Design blocks and cells can also be used to perform early stage analysis and examinations of an electronic design. For example, the process of performing chip planning can be greatly facilitated if the designer or chip planning tool can identify specific blocks or cells that approximate actual blocks or cells that will eventually be used in the final electronic design. Similarly, the process of prototyping can achieve much more accurate results if the prototype circuit design includes blocks and cells that more closely correspond to the actual blocks and cells that will be used in the final circuit design.
However, it is difficult to efficiently and accurately select the blocks or cells that should be used in the early stage design. One of the significant challenges faced by a modern designer is the selection of the specific blocks or cells to use in the early stage design, given the large number of cells and blocks that exist which can possibly be used in the design. This is not a trivial problem given the existence of a very large number of vendors and suppliers of IP blocks in addition to the likely existence of a large number of blocks or cells that a company may have internally developed. The fact that certain designs are only available on specific manufacturing processes adds another layer of complexity in terms of selection.
The normal processes used by organizations to select blocks and cells cannot be efficiently or effectively used to select blocks and cells for early stage designs. This is because the process of generating an early stage design is quite different from the process that is typically used to create final, production-ready electronic design. Since the final electronic design must be fully manufacturable and must correctly operate for its intended functionality and design requirements, an extensive design process is normally undertaken to select exactly the right block or cell for each part of the design, and to verify that the design will manufacture correctly and will function as intended. Therefore, the goal of selecting the most optimal blocks or cells for the design is very important, and a considerable amount of time of resources can and should be taken to make sure that this choice of the design's blocks and cells are correct.
In contrast, the process of generating an early stage design must more heavily weigh the amount of time and resources it takes to select the block or cell for the design against the absolute correctness of the specific block or cell that is chosen. This is because at the early stages of the design process, e.g., for chip planning or prototyping, it is important to be able to obtain fast analysis results and not necessarily as important to utilize a design or model that exactly tracks the final end-product. Moreover, to provide even greater efficiency, the early stage design may use representative blocks/cells throughout a design, rather than specifically tailored and chosen blocks and cells as is the case for a final IC product.